Design Automation Conference,1999,New Orleans,LA,Booth 2757
GENESYS TESTWARE ADDS VHDL SUPPORT TO TESTCORE FAMILY OF SYSTEM ON CHIP TEST PRODUCTS

New Orleans, LA, (June 21, 1999) — Genesys Testware, Inc. today announced the addition of VHDL support to its TestCoreTM family of cores for System on Chip (SOC) test automation. The TestCoreTM family of products include Memory BistCoreTM (Built-In Self-Test (BIST) of embedded memories), Boundary ScanCoreTM (board test, core test integration and test pattern reuse) and Logic BistCoreTM (BIST of hard cores and on-chip logic). Each product in TestCoreTM is a library of parameterized, synthesizable, register-transfer level (RTL) designs. "VHDL is widely used by communications, networking, military and aerospace IC designers. It is the dominant HDL in Europe. Genesys Testware has offered advanced foundry independent RTL SOC test solutions in Verilog to IC designers since 1997. We are committed to fully supporting both Verilog and VHDL users equally", said Bejoy G. Oomman, President of Genesys Testware. TestCoreTM products work seamlessly with logic synthesis tools from Synopsys, Cadence, Mentor Graphics and Synplicity. TestCoreTM products include parameterized self-checking testbenches which can be used to verify the operation of the BIST circuit using any VHDL (IEEE 1076-1993) or Verilog (IEEE 1364-1995) compliant simulator.

"Most IC design companies have multiple IC design teams some of which use Verilog HDL while others use VHDL. Design managers should choose high quality cores which are fully supported in both Verilog and VHDL to reduce training and support costs", said Shridhar Mukund, a senior architect at LightSpeed Semiconductor. TestCoreTM family of products embody the new paradigm of using cores to test cores in a large ASIC or SOC. In a typical SOC test tool process, the user specifies the parameters of the core to a program which generates a test circuit in regular RTL. In the new SOC test core process, the user customizes a highly parameterized RTL test circuit by changing core parameters in Verilog or VHDL. This new paradigm enables revolutionary improvements in ease of use and flexibility by eliminating the RTL test circuit generation process and through RTL integration of test circuitry into an SOC. No tools or libraries are required since it is a completely HDL based solution. RTL test circuits should comply with guidelines for reusable design like the Synopsys/ Mentor Re-use Methodology Manual (RMM) and Virtual Socket Interface (VSI) standards. This allows IC designers to employ advanced design methodologies like formal verification, static timing analysis, and RTL sign-off without interference from test circuitry. TestCoreTM is the only library of test circuits which meet the standards for reusable design. TestCoreTM is also the only test solution which can be seamlessly integrated into IC designer's high level design flow.

Genesys Testware, Inc. today also announced major revisions of all of its products. A highly reconfigurable Built-In Self-Test, Diagnosis and Repair (BISTDR) solution for embedded DRAMs has been added to Memory BistCoreTM . Both address and data repair with multiple user selectable self-repair strategies is also supported in Memory BistCoreTM . Now, it is much more easy for users of Logic BistCoreTM and Memory BistCoreTM to implement multi-frequenzy at-speed testing. At-speed BIST is essential for detecting delay defects which are common in deep sub-micron technology. It is now also possible to generate optimized test patterns in WGL format for 1149.1 compliance checking, pin parametric tests, at-speed scan chain tests, BIST circuit internal tests, and BIST operation from Boundary ScanCoreTM . This allows IC designers to implement a comprehensive SOC test methodology in a process, foundry and tester independent manner.

Genesys Testware, Inc. was founded in October 1995 to improve the productivity of designers of large ICs, by providing comprehensive manufacturing test solutions which promote test reuse. Its unique TestCoreTM family of products has been successfully used in many customer designs. TestCoreTM is licensed as an IC Component Design on a site-wide basis to IC design groups using an EDA tool business model.

For more information on Genesys Testware or its products, please contact:
Bejoy G. Oomman,
Genesys Testware, 181 Ottawa Way,
Fremont, CA 94539. Telephone : 510-661-0791, Fax: 510-498-8734
URL: http:// www. genesystest. com.
bejoygo@ genesystest.com