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International Test Conference, 1998, Washington D.C, Booth 2416
"Core test pattern re-use is essential to the widespread adoption of design re-use", said Hari Surapaneni, President of ChipLogic a major IC design services company. Virtual Components typically have fully registered ports and internal scan. Otherwise, a boundary scan register is wrapped around the core. Core developers create a fictitious design by integrating Boundary ScanCore-VCTM with the core, and generate purely serial scan test patterns using any scan Automatic Test Pattern Generation (ATPG) tool. For RTL (soft) cores, this may be done on a prototype gate level model. The SOC designer uses Boundary ScanCore-VCTM as the test controller and connects each core scan chain separately to it. Boundary ScanCore-VCTM is loaded with the appropriate instructions to manipulate the scan chains of the core as one scan chain at the SOC level. The SOC designer generates only the initialization patterns to select the core scan chains using the Boundary ScanCore-VCTM parameterized testbenches. This enables true core test pattern re-use unlike elaborate pattern hacking tools available from other vendors. The area overhead of adding core test pattern re-use capability is less than 100 gates for each SOC. Boundary ScanCore-VCTM also has features that enable test pattern re-use of legacy non-scan cores. SOC designers can add one or more internal test buses to access legacy cores. Optional instructions to select each legacy core to a test bus are also available in Boundary ScanCore-VCTM. This feature can also be used to simplify silicon debug of embedded processors. Traditional techniques of board debug like logic analysis and in-circuit emulation are ineffective for SOC with embedded processors. The SAMPLE/PRELOAD instruction defined in the IEEE 1149.1 standard cannot be used for embedded logic analysis because it requires the user to exactly specify the time at which chip pins are sampled into the boundary scan register. An optional instruction SAMPLEUNTIL samples the state of the chip pins till a specific trigger condition is met and stops all internal clocks. This allows scan SOC designers to perform embedded logic analysis by using the boundary scan register as a flexible triggering circuit and internal scan chains as serial probe channels. As boards operate at higher frequencies, board interconnects exhibit delay faults due to resistive shorts and incorrect termination. The EXTEST instruction defined in the IEEE 1149.1 standard does not catch such defects due to the long delay between the time at which output pin values are updated and the time at which input pin values are measured. An optional FASTEXTEST instruction is added to Boundary ScanCoreTM for at-speed board interconnect test. Boundary ScanCore-VCTM is available in Verilog HDL and VHDL. Genesys Testware, Inc. was founded in October 1995 to provide complete manufacturing test solutions for deep sub-micron System on Chip designs. Genesys Testware also provides Logic BistCoreTM for Built-In Self-Test (BIST) of hard cores and on-chip logic, and Memory BistCoreTM for implementing Built-In Self-Test Diagnosis and Repair (BISTDR) of embedded memories. For more information on
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