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Design Automation Conference, 1998, San Francisco, CA, Booth 1154
"There is a spectrum of applications for which embedded DRAM is absolutely essential", said Dr. Betty Prince of Memory Strategies International (Sugarland, TX). BIST is the only practical solution for manufacturing test of System on Chip (SOC) designs containing embedded DRAMs. Since the memory array is relatively large the area overhead for BISTDR is minimal (appx. 0.2%). DRAMs have to be tested at-speed due to its dynamic mode of operation. BIST facilitates at speed testing without expensive automatic test equipment (ATE) by embedding a stimulus generator and response analyzer around the DRAM. BIST for embedded DRAMs allows the foundry to use a logic tester to test SOC designs with embedded DRAM. Embedded DRAM users need not tackle the difficult problem of manufacturing test of DRAMs. DRAM cell and compiler developers benefit by the wide-spread adoption of embedded DRAMs by IC designers. Laser based repair of DRAMs with spare rows and columns is widely used to improve the yield of stand-alone DRAM processes. The new Built-In Self-Repair (BISR) feature of Memory BistCoreTM automatically identifies faulty columns as part of the BIST operation. The column failure data can be used to switch out faulty columns using a fuse array for laser repair) or a multiplexor array (for soft repair). Memory BistCoreTM is a library of synthesizable, register-transfer level designs. The user simply choose the appropriate Memory BistCoreTM module based on the desired features and area overhead, add selectors around the embedded memory, instantiate the BIST circuit, synthesize the BIST circuit using the supplied synthesis scripts and verify its operation using the supplied testbenches. Memory BistCoreTM also provides BIST for SRAMS, FIFOs and DRAMs, a flexible architecture which supports all memory test algorithms, and advanced features like fault isolation. It is also easy to use due to its built-in support of scan and ability to directly interface with any IEEE 1149.1 compatible Test Access Port (TAP) controller. Both static and dynamic data retention tests can be added to any march type algorithm. The BIST circuit for DRAMs can be operated in six possible ways corresponding to word, page and burst access modes and data retention test application. The BIST circuit can be easily interfaced with complex DRAMs like JEDEC SDRAMs. The first release of Memory BistCoreTM supports Verilog HDL, and the next release will support VHDL . Genesys Testware, Inc. founded in 1995, provides a complete solution for the manufacturing test of System on Chip designs. Genesys Testware also provides Logic BistCoreTM for BIST of hard cores and on-chip logic, and Boundary ScanCoreTM for implementing boundary scan and core test integration. For more information on
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