Preliminary News Release - International Test Conference 1997, Washington D.C, Booth 1247
GENESYS TESTWARE INTRODUCES INDUTRY'S MOST FLEXIBLE SYNTHESIZABLE CORE LIBRARY FOR TESTING DEEP SUB-MICRON SYSTEMS ON SILICON

WASHINGTON D.C, (NOVEMBER 2, 1997) — Genesys Testware, Inc. today announced the debut release of Logic BistCoreTM - the industry's most flexible synthesizable, parameterized RTL test core library for Built-In Self-Test (BIST) of the logic portion of deep sub-micron systems on silicon. Logic BistCore offers deep sub-micron integrated circuit (IC) designers a flexible, easy-to-use, and feature- rich test synthesis solution. "With Logic BistCoreTM, all IC designers can finally implement logic BIST in all designs regardless of scan type and clocking style without making major changes in their design flow or learning a set of new test tools. Logic BistCore takes advantage of highly parameterized register-transfer level designs which work seamlessly with logic synthesis and scan insertion tools from Synopsys, Cadence, Viewlogic, and Exemplar-Mentor", said Bejoy G. Oomman, President of Genesys Testware. Logic BistCoreTM in conjunction with Memory BistCoreTM and Boundary ScanCoreTM provide industry's most flexible, easy-to-use and feature-rich high level test synthesis (HLTS) solution for deep sub-micron systems on silicon.

Traditionally, complex Automatic Test Equipment (ATE) is used to store and apply tests to each manufactured IC. However, ATE complexity and cost become prohibitive for very complex (millions of transistors), very high speed (>200 Mhz), high pin count (> 500 pins) integrated circuits. BIST technique embeds stimulus generators and response analyzers into the circuit under test itself. BIST provides at-speed testing, and simplifies test equipment. A major change in deep sub-micron IC design methodology is the emphasis on design reuse. BIST encapsulates test capabilities in reusable cores and enables test features to be reused at board and system level.

Logic BistCoreTM is a library of synthesizable, register-transfer level designs. The user simply choose the appropriate Logic BistCoreTM module based on the desired features and area overhead, add selectors around the logic core, instantiate the BIST circuit, synthesize the BIST circuit using the supplied synthesis scripts and verify its operation using the supplied testbenches. Logic BistCoreTM also supports logic cores of all scan types, clocking schemes and reset sequences. Logic BistCoreTM implements several BIST architectures, and advanced features like fault isolation. It is also easy to use due to its built-in support of scan and ability to directly interface with any IEEE 1149.1 compatible Test Access Port (TAP) controller. Logic BistCoreTM supports Verilog HDL now, and will support VHDL in early 1998. Genesys Testware, Inc. aims at providing unique design cores, consulting services and design tools to facilitate effective manufacturing test of deep submicron integrated circuits to increase product quality, while reducing total product cost and product time to market. Genesys Testware, Inc. was founded by Bejoy G. Oomman and Lila M. Mulloth in October, 1995. Genesys Testware provides the TestCoreTM family of synthesizable register-transfer level cores, TestServeTM family of application consulting services in all areas of Design-For-Test, and TestLearnTM family of training classes on chip and board test automation.

For more information on Genesys Testware or its products, please contact:
Bejoy G. Oomman,
Genesys Testware, 181 Ottawa Way,
Fremont, CA 94539. Telephone : 510-661-0791, Fax: 510-498-8734
URL: http:// www. genesystest. com.
bejoygo@ genesystest.com