News Release - Design Automation Conference 1997, Anaheim, CA, Booth 1247
GENESYS TESTWARE INTRODUCES INDUSTRY'S FIRST SYNTHESIZABLE TEST CORE LIBRARY FOR BOARD TEST, IC DEBUG AND SYSTEM BRING-UP

ANAHEIM, D.C, (JUNE 9, 1997) -- Genesys Testware, Inc. today announced the availability of Boundary ScanCoreTM - the industry's first synthesizable test core library for board test, IC debug and system bring-up. Boundary ScanCoreTM joins Memory BistCoreTM (Built-In Self-Test (BIST) solution for embedded memories) in the TestCoreTM family of cores from Genesys Testware. Targeting integrated circuit (IC) designers, Boundary ScanCoreTM offers IC designers a unique solution for testing complex surface mount technology (SMT) boards, controlling on-chip test features like Internal Scan and BIST and debug features like clock control and scan loop-back. "With Boundary ScanCore, IC designers do not have to create a sophisticated Test Access Port (TAP) to test SMT boards, perform first-silicon debug and system bring-up. Since Boundary ScanCore is a library of register-transfer level (RTL) designs in Verilog and VHDL, IC Designers are no longer required to learn a new set of tools. Instead, they can focus on the real challenge of delivering fully debugged ICs, thoroughly tested boards and fully verified systems to the market faster than their competitors. Boundary ScanCore takes advantage of highly parameterized RTL designs which work seamlessly with logic synthesis tools from Synopsys, Cadence, Viewlogic, and Exemplar-Mentor", said Bejoy G. Oomman, President of Genesys Testware.

It is difficult to physically probe the nets of SMT boards during manufacturing test. Boundary Scan provides virtual access to chip pins at the board level. Boundary ScanCore is fully compliant with IEEE 1149.1 standard for boundary scan. Boundary ScanCore supports not only the mandatory features in the TAP to support board testing, but also all optional features to support Internal Scan, BIST and silicon debug. "Large custom or ASIC designs require an advanced TAP which supports board test, IC debug and system bring-up", said Anand Sheel, VP marketing, Advancel Logic, San Jose.

Boundary ScanCoreTM is a library of parameterized, synthesizable RTL designs. The IC designer simply chooses the appropriate Boundary ScanCoreTM module based on the desired features, instantiate the TAP, interconnect the boundary scan chain to the pad ring, and hook up the TAP controller to Internal Scan registers and BIST control registers. Next, the TAP circuit is synthesized using the supplied synthesis scripts and its operation is verified using the supplied testbenches. Boundary ScanCore complements test synthesis solutions from Synopsys, Mentor Graphics, Sunrise-Viewlogic and Genesys Testware. The first release of Boundary ScanCoreTM supports Verilog HDL. The next major release will support VHDL. Genesys Testware, Inc. was founded in October 1995 to provide unique design cores, consulting services and design tools to facilitate effective manufacturing test of deep submicron integrated circuits to increase product quality, while reducing total product cost and product time to market. Genesys Testware provides TestCoreTM family of synthesizable RTL cores, TestServeTM family of application consulting services in all areas of Design-For-Test, and TestLearnTM family of training classes on chip and board test automation.

For more information on Genesys Testware or its products, please contact:
Bejoy G. Oomman,
Genesys Testware, 181 Ottawa Way,
Fremont, CA 94539. Telephone : 510-661-0791, Fax: 510-498-8734
URL: http:// www. genesystest. com.
bejoygo@ genesystest.com