International Test Conference 1996, Washington D.C., Booth 501
GENESYS TESTWARE INTRODUCES INDUSTRY'S FIRST SYNTHESIZABLE MEMORY BUILT-IN SELF-TEST (BIST) CORE LIBRARY TO SHORTEN DESIGN-FOR -TEST CYCLE

WASHINGTON, D.C, (OCTOBER 22, 1996) -- Genesys Testware, Inc. today announced the availability of Memory BistCoreTM - the industry's first synthesizable memory Built-In Self-Test (BIST) core library. Targeting designers of integrated circuits with embedded memories, Memory BistCoreTM offers designers a complete, easy-to-use, flexible and feature rich test synthesis solution. "With Memory BistCore, designers are no longer required to learn a set of new test tools and a new design methodology, but to focus on the real challenge of delivering high performance integrated circuits to the market faster than their competitors. Memory BistCore takes advantage of highly parameterized register-transfer level designs which work seamlessly with logic synthesis tools from Synopsys, Cadence, Viewlogic, Mentor and Exemplar", said Bejoy G. Oomman, President of Genesys Testware. Embedded memories occupy large areas of submicron application specific (ASIC) and custom integrated circuits. Previous techniques like functional testing, memory boundary scan, and multiplexed isolation have high area overhead, high development costs, low fault coverage, and high test application times. This novel BIST scheme for embedded memories achieves very high fault coverage, moderate area overhead, lowtest application times and extremely low development costs. This leads to improved time-to-market, high quality integrated circuits, and reduced total product costs.

Memory BistCoreTM is a library of synthesizable, register-transfer level designs. The user simply choose the appropriate Memory BistCoreTM module based on the desired features and area overhead, add selectors around the embedded memory, instantiate the BIST circuit, synthesize the BIST circuit using the supplied synthesis scripts and verify its operation using the supplied testbenches. Memory BistCoreTM also provides broad support of different memory types, a flexible architecture which supports all memory test algorithms, and advanced features like fault isolation. It is also easy to use due to its built-in support of scan and ability to directly interface with any IEEE 1149.1 compatible Test Access Port (TAP) controller. The first release of Memory BistCoreTM supports Verilog HDL, and the next release in 1997 will support VHDL. Genesys Testware, Inc. aims at providing unique design cores, consulting services and design tools to facilitate effective manufacturing test of deep submicron integrated circuits to increase product quality, while reducing total product cost and product time to market.

Genesys Testware, Inc. was founded by Bejoy G. Oomman and Lila M. Mulloth in October, 1995. Genesys Testware provides the TestCoreTM family of synthesizable register-transfer level cores, TestServeTM family of application consulting services in all areas of Design-For-Test, and TestLearnTM family of training classes on chip and board test automation.

For more information on Genesys Testware or its products, please contact:
Bejoy G. Oomman,
Genesys Testware, 181 Ottawa Way,
Fremont, CA 94539. Telephone : 510-661-0791, Fax: 510-498-8734
URL: http:// www. genesystest. com.
bejoygo@ genesystest.com