New Repair Technology Improves Memory Yield Without Using Fuses LAS VEGAS, Nevada, June 18,
DOLPHIN TECHNOLOGY AND GENESYS TESTWARE ANNOUNCE THE FIRST MEMORY COMPILER TO OFFER DYNAMIC SOFT REPAIR CAPABILITY

LAS VEGAS, Nevada, June 18, 2001—Dolphin Technology, Inc, a leading supplier of embedded memory compilers and custom memories,and Genesys Testware, Inc. a leading provider of embedded test solutions,announced today the first commercially available memory compiler to provide dynamic soft repair technology to improve the yield of large embedded memories.The new product, named RAMpiler+DR, is the result of a joint development effort between Dolphin and Genesys Testware. With RAMpiler+DR the customer can create a large, high performance SRAM that not only has Built-In-Self-Test capability, but also has embedded repair capability to improve yield. This represents a major leap in compiler technology—the melding of compiler technology with embedded test and repair capability.

A typical System on Chip (SoC) contains large amounts of embedded memory. Therefore, SoC yield depends greatly on the embedded memory yield. Dynamic soft repair is a technique that was pioneered by Genesys Testware to improve the yield of large embedded memories. The technique uses special repair logic within the memory array to switch the faulty data or address bits to additional redundant bits that have been compiled into the memory instance. This radical approach to improving memory yield eliminates the need for both laser and electrically programmable fuses. Laser and electrical fuse based repair increases the complexity of physical design of the SOC, requires large up-front investments in new test equipment, large test engineering resources, and complex repair data management. The dynamic soft repair approach eliminates the drawbacks of laser and electrical repair by reconfiguring the memory during power-up. Fabless semiconductor vendors using RAMpiler+DR can greatly increase their profit margins by dramatically reducing the unit cost of the SoC.

“The addition of the RAMpiler+DR product is consistent with our goal of providing our customers with the very latest in technology,” said Mo Tamjidi, President of Dolphin Technology. “We realize that large memories are subject to yield problems. This is why we decided to offer our customers a totally integrated solution consisting of both test and repair capability. We selected the Genesys dynamic soft repair technology because we think it is superior, in many ways, to the older fuse-based technology. We believe that adding this capability gives us a competitive advantage over other memory compilers because now our customers can take advantage of the latest in yield enhancement technology.”

“We are pleased that Dolphin Technology has incorporated our unique dynamic soft repair technology into their latest SRAM memory compiler,” said Bejoy Oomman, President of Genesys Testware. “This will allow Dolphin customers to take advantage of this new technology to improve their memory yield and reduce their manufacturing costs without having to resort to the older fuse-based technology.”

Technical Details
RAMpiler+DR contains Genesys specified multiplexers on the data in and data out lines to support data repair. There is also a special comparator function that is added for doing address repair. By doing this, the delay of the additional repair logic is accounted for in the Dolphin compiled memory so there is no additional delay penalty for implementing the soft repair feature. This provides the customer with a yield improvement scheme that is truly “transparent”. The RAMpiler+DR product supports two redundant data bits and two redundant row address pairs. This will allow the soft repair circuitry to repair almost all the failure mechanisms exhibited by embedded SRAM.
RAMpiler+DR currently is available for single and dual port SRAMs in the UMC 0.13 micron process, IBM 7SF™ process and the TSMC 0.18 micron process. These high density SRAMs can be configured up to 16 Mbits with redundancy. These memories feature synchronous reads/writes, a static design with zero standby current, ability to compile to multiple aspect ratios, row and column redundancy, and small set-up and zero hold times. The compiler outputs consist of behavioral models in Verilog or VHDL, an LVS netlist, Floorplanning and Place & Route models in GDSII and LEF, Synopsys timing files, Power consumption data, and datasheets for each memory.

About Dolphin Technology
Dolphin Technology, Inc. develops and markets high performance embedded memory compilers (Single-port SRAM, Dual-port SRAM, ROM and Register Files), and custom memories (CAM, TLB and register Files). The company is dedicated to providing Silicon IP solutions as well as turnkey custom circuit design, and layout. For further information, visit Dolphin at http://www.dolphin-ic.com

About Genesys Testware
Genesys Testware, Inc. provides a comprehensive suite of embedded test solutions that covers memory test, logic test and boundary scan. Its products are all silicon-proven in various customer designs. For more information, please visit the company’s web site at http://www.genesystest.com# # #