Press Release

For more information contact:

            Bejoy G. Oomman

            Genesys Testware, Inc.

            Tel: 510-661-0791 x258

            Fax: 510-498-8734

            Email: bejoygo@genesystest.com

 

 

FOR IMMEDIATE RELEASE

 

GENESYS TESTWARE INTRODUCES DESIGN FOR MANUFACTURABILITY SOLUTION FOR SYSTEM IC

ChiptestMaker® - an integrated solution to increase yield and test coverage while decreasing test time for system IC

 

San Diego, California, June 7, 2004—Genesys Testware, Inc., announced ChiptestMaker® - a Design For Manufacturability (DFM) solution for system IC today during the Design Automation Conference (DAC) being held here. ChiptestMaker® can be used to increase yield and test coverage while decreasing test time for system IC. ChiptestMaker® was created by integrating the popular ArraytestMaker® and HiertestMaker® tools that have been used successfully in many complex systems IC for many years.

 

“Our customers demanded a more integrated and automated solution to efficiently increase yield and test coverage while decreasing test time for their extremely complex ICs,” said Bejoy Oomman, President of Genesys Testware. “ChiptestMaker provides an integrated Graphical User Interface (GUI) and Tcl scripting environment to satisfy their demands.”

 

ChiptestMaker complements industry standard simulation, logic synthesis, scan insertion and Automatic Test Pattern Generation (ATPG) tools from Cadence, Synopsys and Mentor. The IC designer can generate, verify, synthesize, re-verify and insert test circuits automatically into the IC design using ChiptestMaker. ChiptestMaker minimizes the overhead of test pins and test logic without affecting timing closure.

 

ChiptestMaker have the following key capabilities:

  1. Reliably and cost-effectively increase yield of embedded memory arrays with redundancy from any supplier without using fuses.
  2. Increases test coverage of all types of memory arrays through true at-speed testing.
  3. Increase test coverage of bridging faults in global nets.
  4. Enable yield enhancement by diagnosing bridging faults in global nets.
  5. Decrease test time for logic by reducing the size of scan test patterns, while leveraging customer investment in any scan ATPG.
  6. Increase test coverage for bridging faults in inter-chip wiring on complex boards.

 

ChiptestMaker is available now. ChiptestMaker starts at $90,000 for an annual single-site subscription. ArraytestMaker and HiertestMaker will continue to be available separately. Existing customers can upgrade their current licenses for ArraytestMaker and HiertestMaker to ChiptestMaker.

 

ChiptestMaker will be demonstrated at Booth # 2534 at the San Diego Convention Center during the Design Automation Conference from June 7-10, 2004.

 

About Genesys Testware

Genesys Testware, Inc. provides Design for Manufacturability (DFM) solutions to system IC designers. Genesys Testware is located at 76 Whitney Place, Fremont, CA 94539. For more information, please visit the company’s web site at http://www.genesystest.com

 

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ChiptestMaker, ArraytestMaker and HiertestMaker are trademarks of Genesys Testware, Inc.