Press Release

For more information contact:

            Bejoy Oomman                                               

            Genesys Testware, Inc.                        

            Tel: 510-661-0791x208                                  

            Fax: 510-498-8734                                         

            Email: bejoygo@genesystest.com                  

 

FOR IMMEDIATE RELEASE

GENESYS TESTWARE ADDS TOP-DOWN INSERTION OF TEST AND REPAIR CIRCUITS FOR EMBEDDED MEMORY

 

 

Fremont, California, July 5, 2006  —   Genesys Testware, Inc., a leading supplier of yield, quality and cost optimization tools for nanometer ICs, announced today the addition of  top-down insertion of test and repair circuits for embedded memory to it’s ArraytestMakerTM  product. Currently available tools implement a bottom-up approach to inserting test circuits for embedded memory. System ICs now contain hundreds of memory instances and the number is increasing exponentially with each process generation. The Genesys top-down solution enables system IC designers to insert test and repair circuits for memory in a few days instead of a few weeks required for bottom-up solutions, without compromising efficiency.

 

System IC designers using ArraytestMakerTM can now specify the naming conventions for memories, policies for sharing test and repair circuits between memories and strategies for interconnecting testable memories in a compact script. Policies for sharing are based on memory type, memory bit count, memory hierarchical path, and physical location of memory if available. Strategies for interconnection are based on test circuit functionality, test circuit hierarchical path and the physical location of memories. ArraytestMakerTM automatically models memories, creates testable embedded memories, inserts testable embedded memories into user design, integrates the system of testable embedded memories to the top level of the design, and generates full chip test patterns.

 

“We can efficiently add test and repair circuits to system IC with hundreds of memories using the new automated, top-down, behavioral insertion flow in Genesys ArraytestMaker, that is integrated with popular IC implementation platforms from Synopsys, Cadence and Magma,” said Vinod Sutrave, President of Network Silicon, Inc., a leading IC design services company. “The time for engineering changes before tape-out is reduced from weeks to days using the new flow.”

 

“We are pleased to learn about the addition of top-down insertion of test and repair circuits for embedded memory to Genesys ArraytestMaker”, said Mo Tamjidi, President of Dolphin Technology Inc., a leading provider of high performance embedded memory and memory compiler products. “I am sure that all of our mutual customers will find this new feature very useful”.

 

“Nanometer system IC contain hundreds of memory instances”, said Bejoy Oomman, President of Genesys Testware. “Even inexperienced engineers can now optimize the yield and quality of all memories in a nanometer system IC in a few days time.”

 

Top-down insertion of embedded test and repair circuits for memory is available at no additional cost to existing users of ArraytestMakerTM now.

 

This new feature will be demonstrated during the upcoming 43nd Design Automation Conference that will be held from July 24-27, 2006 at the Moscone Center, San Francisco, California in Exhibitor Booth  #1023.

 

About Genesys Testware

Genesys Testware, Inc. provides tools to improve yield, quality and cost of nanometer ICs. Its products are all silicon-proven in various customer designs. Genesys Testware’s corporate headquarters are located at 76 Whitney Place, Fremont, CA 94539. For more information, please visit the company’s web site at http://www.genesystest.com

ArraytestMaker is a trademark of Genesys Testware, Inc. All other trademarks or registered trademarks are the property of their respective owners.