FOR IMMEDIATE RELEASE

GENESYS TESTWARE ADDS SUPPORT FOR CADENCE ENCOUNTER RTL COMPILER TO CHIPTESTMAKER

Enables mutual customers to easily generate the smallest and fastest embedded test circuits for system ICs

Santa Clara, California, September 14, 2004—Genesys Testware, Inc., announced that it has added support for Cadence® Encounter^TM RTL Compiler^TM to its industry leading ChiptestMaker^® Design For Manufacturability (DFM) solution for system ICs today during the International Cadence User group 2004 Conference being held here. ChiptestMaker^® can be used to increase yield and test coverage while decreasing test time for system IC. ChiptestMaker^® was created by integrating the popular ArraytestMaker^® and HiertestMaker^® tools that have been used successfully in many complex systems IC for many years. This interface enables mutual customers of Cadence Design Systems and Genesys Testware to generate the smallest and fastest embedded test circuits for system ICs.

“Most of the potential customers that we encounter designing system ICs using 90 nanometer technology are using Cadence Encounter RTL Compiler for synthesis,” said Bejoy Oomman, President of Genesys Testware. “We also have many mutual customers who are transitioning to Encounter RTL compiler, who requested that this feature be added to our tools. Customers say they achieve better quality of silicon in less time with less effort using Encounter RTL Compiler.”

System ICs fabricated using 130 nanometer and 90 nanometer processes exhibit many failure mechanisms that can be most effectively detected using at-speed testing. ChiptestMaker test methodology emphasizes at-speed embedded test. Cadence RTL Compiler, with its fast timing convergence capabilities, enable IC designers to create at-speed embedded test circuits with minimum effort.

The ChiptestMaker interface to Encounter RTL Compiler consists of the option to generate complete synthesis scripts with accurate delay and exception constraints to convert RTL embedded test wrappers to gate level. The interface has been validated using standard cell and memory models from IP partners, Artisan Components and Dolphin Technology, for 130 nanometer and 90 nanometer technologies.

ChiptestMaker interface to Encounter RTL Compiler was developed under the Cadence Connections program. Genesys Testware has been a member of the Cadence Connections program since 1996.

ChiptestMaker interface to Encounter RTL Compiler is presently available at no additional cost to all customers. .

ChiptestMaker interface to Encounter RTL Compiler will be demonstrated at Booth #311 at the Santa Clara Convention Center during the International Cadence Usergroup 2004 Conference, Vendor Fair, on September 14, 2004.

Press Release

FOR IMMEDIATE RELEASE

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